Field of the Invention
The present invention relates to a method for the manufacture of a monolithic, static memory cell in which a semiconductor layer of a second conductivity type is arranged on a semiconductor body of a first conductivity type which is provided with a first terminal, in which a region of the first conductivity type is provided at a boundary surface of the semiconductor layer, the region being connected to a first drive line, and in which a first zone of the semiconductor layer adjacent to the region is covered by a gate connected to a second drive line, the gate being separate from the boundary surface by a gate insulator, in which a second zone of the semiconductor layer adjacent to the first zone is covered by a conductive coating connected to a second terminal, and in which the conductive coating is separated from the boundary surface by a thin electrically insulating layer which admits a tunnel current between the boundary surface and the conductive coating.